Вт июн 19, 2012 11:58:54
port map (
DO => DO (7 downto 0), -- 8-bit Data Output
DOP => DO(8), -- 1-bit parity Output
ADDR => adr_reg, -- 11-bit Address Input
CLK => mCLK, -- Clock
DI => sw, -- 8-bit Data Input
DIP => sw(0), -- 1-bit parity Input
EN => EN, -- RAM Enable Input
SSR => RST, -- Synchronous Set/Reset Input
WE => WREN -- Write Enable Input
);
port map (
DO => DO (7 downto 0), -- 8-bit Data Output
DOP => DO (8 downto 8), -- 1-bit parity Output
ADDR => adr_reg, -- 11-bit Address Input
CLK => mCLK, -- Clock
DI => sw, -- 8-bit Data Input
DIP => sw(0 downto 0), -- 1-bit parity Input
EN => EN, -- RAM Enable Input
SSR => RST, -- Synchronous Set/Reset Input
WE => WREN -- Write Enable Input
);
Пт июн 22, 2012 19:49:35