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;******************************************************************************
; *
; This file is a basic code template for code generation on the *
; PIC18F14K50. This file contains the basic code building blocks to build *
; upon. *
; *
; Refer to the MPASM User's Guide for additional information on features *
; of the assembler. *
; *
; Refer to the respective data sheet for additional information on the *
; instruction set. *
; *
;******************************************************************************
; *
; Filename: xxx.asm *
; Date: *
; File Version: *
; Author: *
; Company: *
; *
;******************************************************************************
; *
; Files Required: P18F14K50.INC *
; *
;******************************************************************************
; *
; Notes: *
; *
;******************************************************************************
; *
; Revision History: *
; *
;******************************************************************************
;----------
; PROCESSOR DECLARATION
;----------
LIST P=PIC18F14K50 ; list directive to define processor
#INCLUDE <P18F14K50.INC> ; processor specific variable definitions
;----------
;
; CONFIGURATION WORD SETUP
;
; The 'CONFIG' directive is used to embed the configuration word within the
; .asm file. The lables following the directive are located in the respective
; .inc file. See the data sheet for additional information on configuration
; word settings.
;
;----------
; PIC18F14K50 Configuration Bit Settings
; ASM source line config statements
; CONFIG1L
CONFIG CPUDIV = NOCLKDIV ; CPU System Clock Selection bits (No CPU System Clock divide)
CONFIG USBDIV = OFF ; USB Clock Selection bit (USB clock comes directly from the OSC1/OSC2 oscillator block; no divide)
; CONFIG1H
CONFIG FOSC = HS ; Oscillator Selection bits (HS oscillator)
CONFIG PLLEN = ON ; 4 X PLL Enable bit (Oscillator multiplied by 4)
CONFIG PCLKEN = OFF ; Primary Clock Enable bit (Primary clock is under software control)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRTEN = ON ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOREN = OFF ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 19 ; Brown-out Reset Voltage bits (VBOR set to 1.9 V nominal)
; CONFIG2H
CONFIG WDTEN = OFF ; Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG HFOFST = OFF ; HFINTOSC Fast Start-up bit (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.)
CONFIG MCLRE = OFF ; MCLR Pin Enable bit (RA3 input pin enabled; MCLR disabled)
; CONFIG4L
CONFIG STVREN = OFF ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
CONFIG BBSIZ = OFF ; Boot Block Size Select bit (1kW boot block size)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0 not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1 not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Table Write Protection bit (Block 0 not write-protected)
CONFIG WRT1 = OFF ; Table Write Protection bit (Block 1 not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot block not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit (Block 0 not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit (Block 1 not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot block not protected from table reads executed in other blocks)
;----------
CBLOCK 0x060
zadr
zadr1
zadr2
RESULTHI
RESULTLO
ENDC
; VARIABLE DEFINITIONS
;
;----------
ORG 0x0000 ; processor reset vector
GOTO START ; go to beginning of program
;----------
; HIGH PRIORITY INTERRUPT VECTOR
;----------
ISRH ORG 0x0008
; Run the High Priority Interrupt Service Routine
GOTO HIGH_ISR
;----------
; LOW PRIORITY INTERRUPT VECTOR
;----------
ISRL ORG 0x0018
; Run the High Priority Interrupt Service Routine
GOTO LOW_ISR
;----------
; HIGH PRIORITY INTERRUPT SERVICE ROUTINE
;----------
HIGH_ISR
; Insert High Priority ISR Here
RETFIE FAST
;----------
; LOW PRIORITY INTERRUPT SERVICE ROUTINE
;----------
LOW_ISR
RETFIE
;----------
; MAIN PROGRAM
;----------
START
MOVLB 00Fh
CLRF TRISA
CLRF TRISB
CLRF TRISC
CLRF ADCON1
CLRF ADCON2
CLRF ANSELH
CLRF ANSEL
CLRF LATC
MOVLW 003h
MOVWF LATC,1
MOVLW 00Eh ;left justify, FOSC/64,
MOVWF ADCON2,1 ; & 2TAD ACQ time
MOVLW 000h ;ADC ref = Vdd,Vss
MOVWF ADCON1,1 ;
BSF TRISB,4,1 ;Set RB4 to input
BSF ANSELH,2,1 ;Set RB4 to analog
BSF TRISB,7,1
BSF TRISB,6,1
MOVLW 0xC0
MOVWF WPUB,1
BCF INTCON2,7,1
RAB1
MOVLW 028h ;AN10, ADC off
MOVWF ADCON0,1
MOVLB 000h
MOVLW 0FFh
MOVWF RESULTLO,1
MOVLW 0FFh
MOVWF RESULTHI,1
RAB
MOVLB 00Fh
BTFSS PORTB,7,1
GOTO VKL1
NOP
NOP
GOTO RAB
VKL1
CALL ZADER1
VKL
MOVLB 00Fh
BTFSS PORTB,6,1
GOTO RABNACH
GOTO OSNOV
RABNACH
CALL ZADER1
GOTO RAB1
OSNOV
MOVLB 00Fh
MOVLW 029h ;AN10, ADC on
MOVWF ADCON0,1 ;
CALL ZADER
MOVLB 00Fh
BSF ADCON0,GO,1;Start conversion
ADCPoll
BTFSC ADCON0,GO,1 ;Is conversion done?
GOTO ADCPoll ;No, test again
; Result is complete - store 2 MSbits in
; RESULTHI and 8 LSbits in RESULTLO
MOVFF ADRESH,RESULTHI
MOVFF RESULTHI,WREG
MOVLB 000h
CPFSGT RESULTLO,1
GOTO DOP
GOR
MOVFF RESULTHI,RESULTLO
MOVFF RESULTHI,LATC
CALL ZADER
GOTO VKL
DOP
MOVLB 000h
CPFSEQ RESULTLO,1
GOTO DOP1
GOTO GOR
DOP1
MOVLB 000h
CPFSLT RESULTLO,1
NOP
GOTO VKL
ZADER
MOVLB 000h
MOVLW 04Fh
MOVWF zadr,1
ZAD
DECFSZ zadr,1,1
GOTO ZAD
NOP
NOP
RETURN
ZADER1
MOVLB 000h
MOVLW 0F2h
MOVWF zadr,1
MOVLW 0CCh
MOVWF zadr1,1
MOVLW 03Dh
MOVWF zadr2,1
NOP
NOP
NOP
ZAD1
DECFSZ zadr,1,1
GOTO ZAD1
DECFSZ zadr1,1,1
GOTO ZAD1
DECFSZ zadr2,1,1
GOTO ZAD1
NOP
NOP
RETURN
END
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