Ср окт 09, 2019 17:53:10
NVIC_SetPriority(TIM1_CC_IRQn, 1);
NVIC_EnableIRQ(TIM1_CC_IRQn);
TIM1 ->PSC = 48 - 1;
TIM1 ->ARR = 65535 - 1;
TIM1 ->CCMR1 = (TIM1 ->CCMR1 & ~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC)) |
TIM_CCMR1_CC2S_0;
TIM1 ->CCER |= TIM_CCER_CC2P | TIM_CCER_CC2E;
TIM1 ->DIER |= TIM_DIER_CC2IE;
TIM1 ->CR1 |= TIM_CR1_CEN;
Чт окт 10, 2019 07:19:54
Чт окт 10, 2019 07:31:23
Чт окт 10, 2019 08:26:11
__INLINE void ConfigureTIMxAsInputCapture(void)
{
/* Configure NVIC for TIMx */
/* (1) Enable Interrupt on TIMx */
/* (2) Set priority for TIMx*/
NVIC_EnableIRQ(TIMx_IRQn); /* (1) */
NVIC_SetPriority(TIMx_IRQn,0); /* (2) */
/* (1) Enable the peripheral clock of Timer x */
/* (2) Set PCLK clock prescaler to /16 (111)
set HCLK clock prescaler to /64 (1100) */
/* (3) Enable the peripheral clock of GPIOA */
/* (4) Select alternate function mode on GPIOA pin 8 */
/* (5) Select AF2 on PA8 in AFRH for TIM1_CH1 */
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; /* (1) */
RCC->CFGR |= RCC_CFGR_PPRE | RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2; /* (2) */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (3) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER8)) | (GPIO_MODER_MODER8_1); /* (4) */
GPIOA->AFR[1] |= 0x02; /* (5) */
/* (1) Select the active input TI1 (CC1S = 01),
program the input filter for 8 clock cycles (IC1F = 0011),
select the rising edge on CC1 (CC1P = 0, reset value)
and prescaler at each valid transition (IC1PS = 00, reset value) */
/* (2) Enable capture by setting CC1E */
/* (3) Enable interrupt on Capture/Compare */
/* (4) Enable counter */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0 \
| TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1)*/
TIMx->CCER |= TIM_CCER_CC1E; /* (2) */
TIMx->DIER |= TIM_DIER_CC1IE; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */
}
----------
/**
* @brief This function handles TIM1 interrupt request.
* This interrupt subroutine computes the laps between 2 rising edges
* on T1IC. This laps is stored in the "Counter" variable.
* @param None
* @retval None
*/
void TIM1_CC_IRQHandler(void)
{
uint16_t counter1;
/*
*/
if ((TIMx->SR & TIM_SR_CC1IF) != 0)
{
if ((TIMx->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
{
error = 0xFF;
gap = 0; /* Reinitialize the laps computing */
TIMx->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
return;
}
if (gap == 0) /* Test if it is the first rising edge */
{
counter0 = TIMx->CCR1; /* Read the capture counter which clears the CC1ICF */
gap = 1; /* Indicate that the first rising edge has yet been detected */
}
else
{
counter1 = TIMx->CCR1; /* Read the capture counter which clears the CC1ICF */
if (counter1 > counter0) /* Check capture counter overflow */
{
Counter = counter1 - counter0;
}
else
{
Counter = counter1 + 0xFFFF - counter0 + 1;
}
counter0 = counter1;
error = 0;
}
}
else
{
error = ERROR_WRONG_IT; /* Report an error */
}
}
Чт окт 10, 2019 11:09:02
Чт окт 10, 2019 11:45:26