Чт май 17, 2018 07:48:41
Чт май 17, 2018 07:53:00
//В хидер процессора
#define I2C_CCR_CCR(value) ((I2C_CCR_CCR_Msk & ((value) << I2C_CCR_CCR_Pos)))
#define I2C_CR2_FREQ(value) ((I2C_CR2_FREQ_Msk & ((value) << I2C_CR2_FREQ_Pos)))
//Инициализация
// Ножки SDA и SCL предварительно установить в OUTPUT2_ALT_OPEN_DRAIN
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
I2C1->CR1 = I2C_CR1_SWRST;
I2C1->CR1 = 0;
I2C1->CCR = I2C_CCR_CCR(45); // F = PCLK1/CCR/2
I2C1->CR2 = I2C_CR2_FREQ(36); // Значение PCLK1 [МГц]
I2C1->TRISE = 9;
I2C1->CR1 = I2C_CR1_PE;
Чт май 17, 2018 08:41:39
Чт май 17, 2018 11:38:49
Чт май 17, 2018 12:36:31
Чт май 17, 2018 13:30:53
Чт май 17, 2018 15:07:48
Чт май 17, 2018 15:14:50
Чт май 17, 2018 15:20:24
Чт май 17, 2018 16:36:15
Чт май 17, 2018 18:17:09
Физически то чем адрес от команды отличается?isx писал(а):Там фишка в том, что эта микра не поддерживает адресацию и сразу надо слать команду.
Чт май 17, 2018 18:30:44
Чт май 17, 2018 19:13:12
Чт май 17, 2018 21:38:46
Чт май 17, 2018 22:46:34
Пт май 18, 2018 00:43:28
For instance: in Sm mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, TPCLK1 = 125 ns so CCR must be programmed with 0x28
(0x28 <=> 40d x 125 ns = 5000 ns.)
Пт май 18, 2018 01:58:11
Пт май 18, 2018 05:33:39
Вс май 20, 2018 00:57:17
RCC->CFGR &= ~RCC_CFGR_SW; //Очистка битов выбора источника тактового сигнала
RCC->CR &= ~RCC_CR_PLLON; //Отключаем генератор PLL
RCC->CR &= ~RCC_CR_HSEON;
while((RCC->CR & RCC_CR_HSERDY)!=0) {}
RCC->CR |= RCC_CR_HSION; //Включить генератор HSI
while((RCC->CR & RCC_CR_HSIRDY)==0) {}
RCC->CFGR |= RCC_CFGR_SW_HSI; //Выбрать источником тактового сигнала HSI
/*Тактируем периферию*/
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
/*----------*/
/*Настраиваем Порт B*/
GPIOB->CRL = 0xDD444444;
/*----------*/
I2C1->CR1 = I2C_CR1_SWRST;
I2C1->CR1 = 0;
I2C1->CR2 = 0;
I2C1->OAR1 = 0;
I2C1->OAR2 = 0;
I2C1->SR1 = 0;
I2C1->SR2 = 0;
I2C1->CCR = 0;
I2C1->TRISE = 2;
I2C1->CR1 |=
//I2C_CR1_PE | /*!< Peripheral Enable */
//I2C_CR1_SMBUS | /*!< SMBus Mode */
//I2C_CR1_SMBTYPE | /*!< SMBus Type */
//I2C_CR1_ENARP | /*!< ARP Enable */
//I2C_CR1_ENPEC | /*!< PEC Enable */
//I2C_CR1_ENGC | /*!< General Call Enable */
//I2C_CR1_NOSTRETCH | /*!< Clock Stretching Disable (Slave mode) */
//I2C_CR1_START | /*!< Start Generation */
//I2C_CR1_STOP | /*!< Stop Generation */
//I2C_CR1_ACK | /*!< Acknowledge Enable */
//I2C_CR1_POS | /*!< Acknowledge/PEC Position (for data reception) */
//I2C_CR1_PEC | /*!< Packet Error Checking */
//I2C_CR1_ALERT | /*!< SMBus Alert */
//I2C_CR1_SWRST | /*!< Software Reset */
0;
I2C1->CR2 |=
//I2C_CR2_FREQ | /*!< FREQ[5:0] bits (Peripheral Clock Frequency) ((uint16_t)0x003F)*/
//I2C_CR2_FREQ_0 | /*!< Bit 0 */
//I2C_CR2_FREQ_1 | /*!< Bit 1 */
I2C_CR2_FREQ_2 | /*!< Bit 2 */
//I2C_CR2_FREQ_3 | /*!< Bit 3 */
//I2C_CR2_FREQ_4 | /*!< Bit 4 */
//I2C_CR2_FREQ_5 | /*!< Bit 5 */
//I2C_CR2_ITERREN | /*!< Error Interrupt Enable */
//I2C_CR2_ITEVTEN | /*!< Event Interrupt Enable */
//I2C_CR2_ITBUFEN | /*!< Buffer Interrupt Enable */
//I2C_CR2_DMAEN | /*!< DMA Requests Enable */
//I2C_CR2_LAST | /*!< DMA Last Transfer */
0;
I2C1->OAR1 |=
//I2C_OAR1_ADD1_7 | /*!< Interface Address ((uint16_t)0x00FE)*/
//I2C_OAR1_ADD8_9 | /*!< Interface Address ((uint16_t)0x0300)*/
//I2C_OAR1_ADD0 | /*!< Bit 0 */
//I2C_OAR1_ADD1 | /*!< Bit 1 */
//I2C_OAR1_ADD2 | /*!< Bit 2 */
//I2C_OAR1_ADD3 | /*!< Bit 3 */
//I2C_OAR1_ADD4 | /*!< Bit 4 */
//I2C_OAR1_ADD5 | /*!< Bit 5 */
//I2C_OAR1_ADD6 | /*!< Bit 6 */
//I2C_OAR1_ADD7 | /*!< Bit 7 */
//I2C_OAR1_ADD8 | /*!< Bit 8 */
//I2C_OAR1_ADD9 | /*!< Bit 9 */
//I2C_OAR1_ADDMODE | /*!< Addressing Mode (Slave mode) */
0;
I2C1->OAR2 |=
//I2C_OAR2_ENDUAL | /*!< Dual addressing mode enable */
//I2C_OAR2_ADD2 | /*!< Interface address ((uint8_t)0xFE)*/
0;
//I2C1->DR = I2C_DR_DR; /*!< 8-bit Data Register ((uint8_t)0xFF)*/
I2C1->CCR |= 20 |
//I2C_CCR_CCR | /*!< Clock Control Register in Fast/Standard mode (Master mode) ((uint16_t)0x0FFF)*/
//I2C_CCR_DUTY | /*!< Fast Mode Duty Cycle */
//I2C_CCR_FS | /*!< I2C Master Mode Speed Selection */
0;
/*For instance: in Sm mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, TPCLK1 = 125 ns so CCR must be programmed with 0x28 (40)
(0x28 <=> 40d x 125 ns = 5000 ns.)*/
I2C1->TRISE = 9;
//I2C_TRISE_TRISE; /*!< Maximum Rise Time in Fast/Standard mode (Master mode) ((uint8_t)0x3F)*/
I2C1->CR1 |= I2C_CR1_PE;
/*----------*/
__enable_irq ();
while(1)
{
I2C1->CR1 |= I2C_CR1_START;
while (!(I2C1->SR1 & I2C_SR1_SB)){;}
Test_1 = I2C1->SR1;
I2C1->DR = TM1637_DSC;
Test_1 = 1;
while(1){}
}
}
Вс май 20, 2018 08:26:49