Вт мар 28, 2017 21:00:00
module filter(
input wire data,
input wire clk,
output reg signal,
output reg [1:0]state
);
always @ (posedge clk)
begin
case(state)
0: state <= 1;
1: state <= 2;
2: state <= 3;
3: state <= 0;
endcase
end
always @ (state)
begin
case(state)
0: signal <= signal;
1: signal <= data;
2: signal <= signal;
3: signal <= signal;
endcase
end
endmodule
Ср мар 29, 2017 22:37:00
module filter(
input wire data,
input wire clk,
output reg signal,
output reg [1:0]state
);
always @ (posedge clk)
begin
case(state)
0: begin state <= 1; signal <= data; end;
1: begin state <= 2; signal <= signal; end;
2: begin state <= 3; signal <= signal; end;
3: begin state <= 0; signal <= signal; end;
endcase
end
endmodule