Вс апр 02, 2017 16:49:39
module modulesd
(
input hz,
input reset,
output reg clk = 1'b0
);
reg [0:47] cmd;
reg [23:0] counter = 24'b0;
//----------
always @(posedge reset or posedge hz)
begin
if(reset)
counter <= 24'b0;
else
begin
counter <= counter + 1'b1;
if(counter+1==24'd2)
begin
counter <= 24'b0;
clk <= ~clk;
end
end
end
//----------
endmodule
Вт апр 18, 2017 00:57:38