Сб май 20, 2017 15:59:29
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity test is
port(
clk, r: in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
p : out std_logic_vector(15 downto 0)
);
end test;
--}} End of automatically maintained section
architecture test of test is
begin
process(clk,r,a,b)
variable pv,bp: std_logic_vector(15 downto 0);
begin
pv:= "0000000000000000";
bp:= "00000000" & b;
if r='1' then
pv:="0000000000000000";
p<=pv;
else
if clk'event and clk = '1' then
for i in 0 to 7 loop
if a(i) = '1' then
pv:= pv+bp;
p<=pv;
end if;
bp:= bp(14 downto 0) & '0';
end loop;
end if;
end if;http://radiokot.ru:5050/elecir/
end process;
end test;
Вс июл 23, 2017 02:29:11