Ср сен 27, 2017 21:48:51
module delay
(
input wire clk,
input wire sgn,
output reg out
);
localparam phase = 1;
reg[7:0] pos_cnt = 0,
neg_cnt = 0;
always @ (posedge clk)
begin
if (sgn)
begin
pos_cnt <= pos_cnt + 1;
if (neg_cnt > phase) neg_cnt <= neg_cnt - 1;
else
begin
neg_cnt <= 0;
out <= 1;
end
end
else
begin
neg_cnt <= neg_cnt + 1;
if (pos_cnt > phase) pos_cnt <= pos_cnt - 1;
else
begin
pos_cnt <= 0;
out <= 0;
end
end
end
endmodule
Ср сен 27, 2017 22:02:41
Ср сен 27, 2017 22:09:15
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