Вт ноя 21, 2017 11:13:39
Вт ноя 21, 2017 16:21:19
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lab4 is
Port ( CLK : in STD_LOGIC;
CE, SRST : in STD_LOGIC;
Q: out STD_LOGIC);
end lab4;
architecture rtl of lab4 is
signal N: STD_LOGIC_VECTOR(4 downto 0);
signal i: integer range 0 to 5;
begin
process(CLK) begin
if rising_edge(CLK) then
if SRST = '1' then
i<=5;
N<="10011";
Q<='0';
else
if CE = '1' then
i<=0;
end if;
if i=5 then
Q<='0';
else
i<=i+1;
Q<=N(i);
end if;
end if;
end if;
end process;
end rtl;
Вт ноя 21, 2017 23:59:30
Ср ноя 22, 2017 15:56:25
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY lab_test IS
END lab_test;
ARCHITECTURE behavior OF lab_test IS
COMPONENT lab4
PORT(
CLK : IN std_logic;
CE : IN std_logic;
SRST : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal CE : std_logic := '0';
signal SRST : std_logic := '1';
--Outputs
signal Q : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lab4 PORT MAP (
CLK => CLK,
CE => CE,
SRST => SRST,
Q => Q
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
srst<='0';
wait for CLK_period*10;
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
ce<='1';
wait until rising_edge(clk);
ce<='0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
ce<='1';
wait until rising_edge(clk);
ce<='0';
wait until rising_edge(clk);
-- insert stimulus here
wait;
end process;
END;
Ср ноя 22, 2017 21:15:04