Пт фев 01, 2013 17:50:31
Пт фев 01, 2013 19:10:00
module bidirec (oe, clk, inp, outp, bidir);
// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;
// Always Construct
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule
Чт авг 22, 2013 22:59:01
module MemInit (
//Тактирование
input wire mem_clk_133MHz,
input wire mem_clk_lock,
input wire nreset,
output wire init_done,
//output wire [2:0] init_cmd,
//output wire [21:0] init_adr,
input wire cmd_ack
);
/*****************************************************************/
//Описание состояний
localparam [3:0]
state_begin = 4'b0000,
state_loadreg1 = 4'b0001,
state_iwait = 4'b0010,
state_prech = 4'b0011,
state_prwait = 4'b0100,
state_fautor = 4'b0101,
state_fwait = 4'b0110,
state_sautor = 4'b0111,
state_swait = 4'b1000,
state_loadmr = 4'b1001,
state_loadreg2 = 4'b1010,
state_done = 4'b1111;
/*****************************************************************/
//регистры
reg [3:0] state = state_begin;
reg [3:0] next_state = state_begin;
reg init_done_reg = 0, next_init_done_reg;
reg [31:0] cycle_counter = 0;
reg [31:0] next_cycle_counter = 0;
assign init_done = init_done_reg;
/*****************************************************************/
//Тактирование
wire clk;
assign clk = mem_clk_133MHz & mem_clk_lock;
always @(posedge clk or negedge nreset) begin
if(!nreset) begin //Сброс
state <= state_begin;
init_done_reg <= 0;
end
else begin //Нормальная работа
state <= next_state;
init_done_reg <= next_init_done_reg;
cycle_counter <= next_cycle_counter;
end
end
/*****************************************************************/
//Машинка состояний
always @* begin
next_state = state;
next_init_done_reg = init_done_reg;
next_cycle_counter = cycle_counter + 32'b1;
case (state)
state_begin:
begin
next_cycle_counter = 0;
next_state = state_iwait;
end
state_iwait:
begin
if(cycle_counter >= 32'd133000) next_state = state_done;
end
state_done:
begin
next_init_done_reg = 1;
end
default:
begin
next_state = state_begin;
next_init_done_reg = 0;
end
endcase
end
endmodule
Вт окт 22, 2013 18:42:43
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Pawel91 писал(а):Почему задержка не срабатывает?
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Pawel91 писал(а):Я вот как раз и делал моделирование
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