Ср фев 27, 2013 11:16:51
module D3 (WR,RES,RD,CS,DAT,A,OUT,PWR);
input RES;
input wire [3:0] A;
input wire WR, RD, CS,PWR;
inout wire [7:0] DAT;
output wire [8:1] OUT;
reg [7:0] D;
reg [8:1] INREG;
always @(negedge RD or negedge WR)
case (A)
4'b0000: D <= 8'b00100000;
4'b0001: D <= 8'b00010110;
4'b0010: D <= 8'b00001000;
4'b0011: D <= 8'b00001000;
4'b0100: D <= 8'b00001001;
4'b1000: D <= INREG;
4'b1010: D <= {4'b0, PWR, 3'b001};
default: D = 8'b00000000;
endcase
always @(negedge WR or negedge RES)
begin
if (RES == 0)
INREG <= 0;
else if (!CS && A == 8)
INREG <= DAT;
end
assign DAT[7:0]=(!CS&!RD)?D[7:0]:8'bz;
assign OUT[1]=(INREG[1])?8'b0:8'bz;
assign OUT[2]=(INREG[2])?8'b0:8'bz;
assign OUT[3]=(INREG[3])?8'b0:8'bz;
assign OUT[4]=(INREG[4])?8'b0:8'bz;
assign OUT[5]=(INREG[5])?8'b0:8'bz;
assign OUT[6]=(INREG[6])?8'b0:8'bz;
assign OUT[7]=(INREG[7])?8'b0:8'bz;
assign OUT[8]=(INREG[8])?8'b0:8'bz;
endmodule
Ср фев 27, 2013 14:55:22
Ср фев 27, 2013 14:57:17
Ср фев 27, 2013 17:39:12
Ср фев 27, 2013 22:02:40
Kavka писал(а): Либо таймер в ПЛИС.
input clk;
wire reset;
reg[15:0] count;
reset = (count < 16'hFFFF);
always @(posedge clk) if(reset) count <= count+1'b1;
Чт фев 28, 2013 07:10:52