Вт окт 08, 2013 14:22:22
Вт окт 08, 2013 20:32:43
11001001b
* 101b
----------
11001001b
+ 00000000 b
+ 11001001 b
----------
1111101101b
Ср окт 09, 2013 14:26:06
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mult2 is
Port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
sx : in STD_LOGIC;
p1 : out STD_LOGIC;
p2 : out STD_LOGIC);
end mult2;
architecture Behavioral of mult2 is
COMPONENT add1
PORT(
a : IN std_logic;
b : IN std_logic;
s : OUT std_logic;
c : OUT std_logic
);
END COMPONENT;
signal s1,s2 : std_logic;
begin
p1 <= a1 and sx;
s1 <= a1 and a2;
s2 <= a2 and sx;
o1: add1 port map (s1,p2,s2);
o2: add1 port map (s2);
end Behavioral;
Ср окт 09, 2013 15:04:41
Ср окт 09, 2013 15:27:19
Ср окт 09, 2013 16:04:17