Пн июл 16, 2018 09:00:43
Пн июл 16, 2018 23:31:35
Вт июл 17, 2018 12:17:05
Чт авг 09, 2018 18:01:47
void TIM1_Init(void)
{
GPIOC->DDR |= GPIO_PIN_4;
GPIOC->CR1 |= GPIO_PIN_4;
GPIOC->CR2 |= GPIO_PIN_4;
CLK->PCKENR1 |= CLK_PCKENR1_TIM1; //16MHz
TIM1->CR1 &= ~TIM1_CR1_CEN; //OFF
TIM1->CR1 |= TIM1_CR1_ARPE;
TIM1->PSCRH = 0x00;
TIM1->PSCRL = 0x08; // 16MHz/8 = 2MHz
TIM1->ARRH = 0x4e; //2MHz/20000 = 100Hz частота шима
TIM1->ARRL = 0x20;
//D = 100% = 20000
//D = 50% = 10000
TIM1->CCMR4 |= 0x68; //PWM MODE, Output compare 4 preload enable
TIM1->CCER2 &= ~TIM1_CCER2_CC4P; //PC4
TIM1->CCER2 |= TIM1_CCER2_CC4E;
TIM1->BKR |= TIM1_BKR_MOE;
TIM1->CCR4H = 0x00; //D=0%
TIM1->CCR4L = 0x00;
TIM1->IER &= ~TIM1_IER_UIE;
TIM1->CR1 |= TIM1_CR1_CEN; //ON;
TIM1->CCR4H = 0x3a; //15000, D = 75%
TIM1->CCR4L = 0x98;
}
Чт авг 09, 2018 18:35:52
Чт авг 09, 2018 20:07:22
Чт авг 09, 2018 22:52:46
Пт авг 10, 2018 15:34:12
SDCC : mcs51/z80/z180/r2k/r3ka/gbz80/tlcs90/ds390/pic16/pic14/TININative/ds400/hc08/s08/stm8 3.4.0 #8981 (Jan 10 2015) (Linux)
published under GNU General Public License (GPL)
Пт авг 10, 2018 16:49:45
void TIM1_init(void) // Настройка таймера 1
{
//PWM output signal frequency = TIM1 counter clock/(TIM1_ARR + 1)
//Channel x duty cycle = [TIM1_CCRxx/(TIM1_ARR + 1)] * 100
TIM1->PSCRH = 0x00;
TIM1->PSCRL = 0x00;
TIM1->ARRH = 0x0F;
TIM1->ARRL = 0x9F;
TIM1->CCMR1 |= (uint8_t)0x60; //110: PWM mode 1 - In up-counting, channel 1 is active as long as TIM1_CNT < TIM1_CCR1,
TIM1->CCER1 |= TIM1_CCER1_CC1E; //CH1 compare Enable
TIM1->CCR1H = 0x07;
TIM1->CCR1L = 0xD0;
TIM1->CR1 |= TIM1_CR1_CEN;
TIM1->BKR |= TIM1_BKR_MOE; // OC and OCN outputs are enabled if their respective enable bits are set (CC/E in Tim1_CCERi)
}
Пт авг 10, 2018 17:34:37
#include "stm8s.h"
void TIM1_Init(void)
{
GPIOC->DDR |= GPIO_PIN_4;
GPIOC->CR1 |= GPIO_PIN_4;
GPIOC->CR2 |= GPIO_PIN_4;
CLK->PCKENR1 |= CLK_PCKENR1_TIM1; //16MHz
TIM1->CR1 &= ~TIM1_CR1_CEN; //OFF
TIM1->CR1 |= TIM1_CR1_ARPE;
TIM1->PSCRH = 0x00;
TIM1->PSCRL = 0x08; // 16MHz/8 = 2MHz
TIM1->ARRH = 0x4e; //2MHz/20000 = 100Hz частота шима
TIM1->ARRL = 0x20;
//D = 100% = 20000
//D = 50% = 10000
TIM1->CCMR4 |= 0x68; //PWM MODE, Output compare 4 preload enable
TIM1->CCER2 &= ~TIM1_CCER2_CC4P; //PC4
TIM1->CCER2 |= TIM1_CCER2_CC4E;
TIM1->BKR |= TIM1_BKR_MOE;
TIM1->CCR4H = 0x00; //D=0%
TIM1->CCR4L = 0x00;
TIM1->IER &= ~TIM1_IER_UIE;
TIM1->CR1 |= TIM1_CR1_CEN; //ON;
TIM1->CCR4H = 0x3a; //15000, D = 75%
TIM1->CCR4L = 0x98;
}
int main( void )
{
CLK->CKDIVR = 0;
TIM1_Init();
while (1);
}
Пт авг 10, 2018 19:14:52
Пт авг 10, 2018 19:55:02
Сб авг 11, 2018 13:32:24
Сб авг 11, 2018 13:47:48
Сб авг 11, 2018 14:05:02
Сб авг 11, 2018 14:41:13
Сб авг 11, 2018 15:34:39
Вс авг 26, 2018 12:23:28
Clear_Fl_Ext_D EXTI_CR1_PDIS=0;EXTI_CR1_PDIS=0x3;
11.9.4 Port x control register 1 (Px_CR1)
Address offset: 0x03
Reset value: 0x00 except for PD_CR1 which reset value is 0x02.
Пн сен 03, 2018 07:47:11
Пн сен 03, 2018 11:29:04
void copy_array(uint8_t * buf)
{ uint8_t test,i;
for(i=0;i<8;i++)
{
test= *buf++;
}
}
uint8_t my_array[20]={1,45,68,34,78,23,98,56,3,0,165};
copy_array(my_array);
void copy_array(uint8_t * buf)
{ uint8_t test,i;
for(i=0;i<8;i++)
{
test= buf[i];
}
}
copy_array(&my_array[0]);