Чт май 12, 2022 17:07:02
Чт май 12, 2022 17:52:08
Чт май 12, 2022 18:14:22
Вт июл 12, 2022 16:36:57
Вт июл 12, 2022 16:39:27
Вт июл 12, 2022 16:41:16
Ср июл 13, 2022 23:45:46
Отладка в ОЗУ?dim3740 писал(а):И "заодно" не могу и (не хочу прошивать), потому что прошивку надо же отлаживать многократно.
Чт июл 14, 2022 00:19:12
модуль/плата впаяна в плату
Вт июл 19, 2022 12:51:05
Сб дек 24, 2022 20:50:26
Сб дек 24, 2022 21:23:19
Сб дек 24, 2022 21:27:25
Сб дек 24, 2022 21:39:26
Сб дек 24, 2022 22:07:34
Сб дек 24, 2022 22:18:58
Вс дек 25, 2022 16:45:59
Вс дек 25, 2022 16:57:57
Пн янв 16, 2023 18:35:15
void Send_CMD(uint8_t dat)
{ //Otpravka komand
GPIOB->ODR &= ~(1<<7); //ChipSelect loy
GPIOB->ODR &= ~(1<<6); //DC LoyLevel
SPI1->CR1 &= ~SPI_CR1_DFF;
while (!(SPI1->SR & SPI_SR_TXE));
SPI1->DR = dat;
while (!(SPI1->SR & SPI_SR_TXE));
while ((SPI1->SR & SPI_SR_BSY));
GPIOB->ODR |= (1<<7); //ChipSelect Up
}
void Send_DAT(uint8_t dat){ // danue 8 bit
GPIOB->ODR &= ~(1<<7); //ChipSelect loy
GPIOB->ODR |= (1<<6); //DC UpLevel
SPI1->CR1 &= ~SPI_CR1_DFF;
while (!(SPI1->SR & SPI_SR_TXE));
SPI1->DR = dat;
while (!(SPI1->SR & SPI_SR_TXE));
while ((SPI1->SR & SPI_SR_BSY));
GPIOB->ODR |= (1<<7); //ChipSelect Up
}
void Send_DAT16(uint16_t dat){ // danue 16 bit
GPIOB->ODR &= ~(1<<7); //ChipSelect loy
GPIOB->ODR |= (1<<6); //DC UpLevel
SPI1->CR1 |= SPI_CR1_DFF;
while (!(SPI1->SR & SPI_SR_TXE)){};
SPI1->DR = dat;
while (!(SPI1->SR & SPI_SR_TXE)){};
while ((SPI1->SR & SPI_SR_BSY)){};
GPIOB->ODR |= (1<<7); //ChipSelect Up
}
void LCD_Init(){
SPI1->CR1 |= SPI_CR1_SPE;//On Spi1
GPIOB->ODR |= (1<<4); //RST Hay
delay(15);
GPIOB->ODR &= ~(1<<4); //RST loy
delay(15);
GPIOB->ODR |= (1<<4); //RST Hay
delay(15);
Send_CMD(0x01);//Sbros nastroek
delay(50);
Send_CMD(0x28);//Programnoe wukl
Send_CMD(0xC0);//Obuchnaja pitanie
Send_CMD(0x11);//SlipOut
delay(150);
Send_CMD(0x29);//DispOn
Send_CMD(0x3A); //Format peredachi piksela
Send_DAT(0x55);
Send_CMD(0x20);//Vukl inversiu
Send_CMD(0x36);//hz
Send_DAT(0x80);
Send_DAT(0x40);
Send_DAT(0x08);
Send_DAT(0x20);
}
void SetWindow(uint16_t startX, uint16_t startY, uint16_t stopX, uint16_t stopY) {
Send_CMD(0x2A);
Send_DAT(startX >> 8);
Send_DAT(startX);
Send_DAT(stopX >> 8);
Send_DAT(stopX);
Send_CMD(0x2B);
Send_DAT(0x00);
Send_DAT(startY);
Send_DAT(stopY);
}
void bufer()
{
uint16_t x = 0, y = 0;
SetWindow(0, 0, 240, 320);
Send_CMD(0x2C);
while(y++ < 320)
{
x=0;
while(x++ < 240)
{
Send_DAT16(0xFFE0);//0xFFE0
}
}
}
#define RCC_PLLCFGR_PLLP_div2 (0x0U << RCC_PLLCFGR_PLLP_Pos)
#define RCC_PLLCFGR_PLLP_div4 (0x1U << RCC_PLLCFGR_PLLP_Pos)
#define RCC_CFGR_MCO2_HSE (0x2U << RCC_CFGR_MCO2_Pos)
#define RCC_CFGR_MCO2PRE_div1 (0x0U << RCC_CFGR_MCO2PRE_Pos)
#define RCC_CFGR_MCO1PRE_div1 (0x0U << RCC_CFGR_MCO1PRE_Pos)
#define RCC_CFGR_I2SSRC_PLLI2S (0x0U << RCC_CFGR_I2SSRC_Pos)
#define RCC_CFGR_MCO1_HSE (0x2U << RCC_CFGR_MCO1_Pos)
#include <stddef.h>
#include "stm32f411xe.h"
#ifdef __cplusplus
extern "C" {
#endif
int __low_level_init(void)
{
//Kvarc 25MHz, Proc 100MHzbegin
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16) | RCC_CR_HSION | RCC_CR_HSEON;
while(!(RCC->CR & RCC_CR_HSERDY));
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | _VAL2FLD(RCC_PLLCFGR_PLLQ,4) | _VAL2FLD(RCC_PLLCFGR_PLLN,192) | _VAL2FLD(RCC_PLLCFGR_PLLM,25) | RCC_PLLCFGR_PLLP_div2;
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16) | RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_PLLON;
while(!(RCC->CR & RCC_CR_PLLRDY));
RCC->CFGR = RCC_CFGR_MCO2_HSE | RCC_CFGR_MCO2PRE_div1 | RCC_CFGR_MCO1PRE_div1 | RCC_CFGR_I2SSRC_PLLI2S | RCC_CFGR_MCO1_HSE
| _VAL2FLD(RCC_CFGR_RTCPRE,8) | RCC_CFGR_PPRE2_DIV1 | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
//*///Kvarc 25MHz, Proc 100MHz End
//Timer begin
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;// Taktirovanie Timer 2
__enable_irq ();
//Timer end
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; //Taktirovanie SPI1
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;//Taktirovanie Port B
GPIOB->AFR[0] |= 0x00505000;
GPIOB->MODER |= ( GPIO_MODER_MODER4_0 | GPIO_MODER_MODER6_0 | GPIO_MODER_MODER7_0 | GPIO_MODER_MODER8_0 | GPIO_MODER_MODER10_0 ); // Port B Vihod
GPIOB->PUPDR |= ( GPIO_PUPDR_PUPD4_1 | GPIO_PUPDR_PUPD6_1 | GPIO_PUPDR_PUPD7_1 | GPIO_PUPDR_PUPD8_1 | GPIO_PUPDR_PUPD10_1 ); // Port B Vihod
GPIOB->MODER |= (GPIO_MODER_MODER3_1 | GPIO_MODER_MODER5_1);
GPIOB->OSPEEDR |= (3<<10)|(3<<6)|(3<<8)|(3<<12)|(3<<14)|(3<<19); // HIGH Speed for PA5, PA6, PA7, PA9
SPI1->CR1 |= (SPI_CR1_MSTR | SPI_CR1_SSM | SPI_CR1_SSI);
NVIC_EnableIRQ(TIM2_IRQn); //Prerivania
return 0;
}
#ifdef __cplusplus
}
#endif
Пн янв 16, 2023 19:03:09
Пн янв 16, 2023 19:10:46
static uint8_t flagon = 1;
void delay(uint32_t _delay){
TIM2->PSC =9600;
TIM2->ARR = _delay*10;//ms
TIM2->CR1 |= TIM_CR1_CEN;
TIM2->DIER |= TIM_DIER_UIE;
flagon = 1;
while(flagon);}
void TIM2_IRQHandler(void)
{
TIM2->SR &= ~TIM_SR_UIF;
TIM2->CR1 &= ~TIM_CR1_CEN;
flagon = 0;
}
//Draiver displeja, svistok stm32F411CEU6, TFT 126x160 ST7735
/*3.3v PB3(SPI1_SCK)-SCL
PB5(SPI1_MOSI)-SDA
PB4-RES
PB6-DC (Dannye|Komandy)
PB7-CS
PB8-BL (Pitanie???)
PB10-HL na GND
*/
#include <stddef.h>
#include "stm32f411xe.h"
#include "displey.h"
int main()
{
//GPIOB->ODR |= 0x400;//On svetodiod
GPIOB->ODR |= 0x100;//On podsvetka
LCD_Init();
//bufer();
while(1){
delay(1000);//1s
// GPIOB->ODR |= (1<<8);//On svetodiod
// delay(1000);//1s
// GPIOB->ODR &= ~(1<<8);//On svetodiod
} }
void SystemInit(void){}
//Kvarc 25MHz, Proc 100MHzbegin
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16) | RCC_CR_HSION | RCC_CR_HSEON;
while(!(RCC->CR & RCC_CR_HSERDY));
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | _VAL2FLD(RCC_PLLCFGR_PLLQ,4) | _VAL2FLD(RCC_PLLCFGR_PLLN,192) | _VAL2FLD(RCC_PLLCFGR_PLLM,25) | RCC_PLLCFGR_PLLP_div2;
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16) | RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_PLLON;
while(!(RCC->CR & RCC_CR_PLLRDY));
RCC->CFGR = RCC_CFGR_MCO2_HSE | RCC_CFGR_MCO2PRE_div1 | RCC_CFGR_MCO1PRE_div1 | RCC_CFGR_I2SSRC_PLLI2S | RCC_CFGR_MCO1_HSE
| _VAL2FLD(RCC_CFGR_RTCPRE,8) | RCC_CFGR_PPRE2_DIV1 | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;