Чт янв 27, 2022 17:08:16
Чт янв 27, 2022 17:42:06
Чт янв 27, 2022 18:03:03
Чт янв 27, 2022 18:11:30
Чт янв 27, 2022 18:27:54
Чт янв 27, 2022 18:43:38
Чт янв 27, 2022 21:16:07
LDR.W R4,??DataTable2
MOVS R0,#+2
STR R0,[R4, #+0]
MOVS R1,#+2
STR R1,[R4, #+4]
Чт янв 27, 2022 21:29:15
Пт янв 28, 2022 07:22:43
Пт янв 28, 2022 07:32:15
Пт янв 28, 2022 13:01:47
Пт янв 28, 2022 13:40:47
Пт янв 28, 2022 14:12:23
void RCC_init(void)
{
FLASH->ACR |= FLASH_ACR_PRFTEN ;
//FLASH->ACR &=~ (FLASH_ACR_LATENCY_2WS) ;
FLASH->ACR |= FLASH_ACR_LATENCY_3WS ;
//PWR->CR|= PWR_CR_VOS;
RCC->CR|=RCC_CR_HSEON; // Enable HSE
while (!(RCC->CR & RCC_CR_HSERDY));
RCC->CR|=RCC_CR_CSSON;
RCC->PLLCFGR |=RCC_PLLCFGR_PLLSRC_HSE ;
RCC->PLLCFGR |= PLL_M>>RCC_PLLCFGR_PLLM_Pos |PLL_N << RCC_PLLCFGR_PLLN_Pos|PLL_P>>RCC_PLLCFGR_PLLP_Pos |RCC_PLLCFGR_PLLSRC_HSE;
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;// ��������� ���� AHB
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;// ��������� ���� APB1
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
RCC->CR |= RCC_CR_PLLON; // enable PLL
while(!(RCC->CR & RCC_CR_PLLRDY))
{
}
RCC->CFGR |= RCC_CFGR_SW_PLL; // select source SYSCLK = PLL
while(!(RCC->CFGR& RCC_CFGR_SWS_PLL))
{
}
}
Пт янв 28, 2022 19:13:34
ivan dimir писал(а):А как правильно настроить параметры .Расчитать параметы вроде посчитал перепрвил.Не работает.
///system_f746
RCC->CR = RCC_CR_HSION | RCC_CR_HSEON;
RCC->PLLCFGR = _VAL2FLD(RCC_PLLCFGR_PLLM, 12)| // Primary frequency divider (2-63)
_VAL2FLD(RCC_PLLCFGR_PLLN, 324)| // Clock multiplier for PLLCLK (50-432)
_VAL2FLD(RCC_PLLCFGR_PLLP, 0)| // The last divisor for PLLCLK n[2,4,6,8]
_VAL2FLD(RCC_PLLCFGR_PLLQ, 9)| // Divisor for USB, SDMMC, and RNG (2-15)
RCC_PLLCFGR_PLLSRC_HSE;
RCC->PLLSAICFGR = _VAL2FLD(RCC_PLLSAICFGR_PLLSAIN, 252)| // PLLN frequency multiplication PLLSAI (50-432)
_VAL2FLD(RCC_PLLSAICFGR_PLLSAIP, 0)| // P division factor for USB,RNG,SDMMC(48MHz) n[2,4,6,8]
_VAL2FLD(RCC_PLLSAICFGR_PLLSAIQ, 15)| // Q division factor for SAI clock (2-15)
_VAL2FLD(RCC_PLLSAICFGR_PLLSAIR, 3); // R division factor for LCD clock (2-7)
RCC->CR |= RCC_CR_PLLSAION | RCC_CR_PLLON; // PLL enable
RCC->CFGR = RCC_CFGR_HPRE_DIV1| // Divisor SYSCLK to HCLK
RCC_CFGR_PPRE1_DIV4| // Divisor HCLK to the 1 periphery
RCC_CFGR_PPRE2_DIV2| // Divisor HCLK to the 2 periphery
_VAL2FLD(RCC_CFGR_RTCPRE,20)| // HSE division factor for RTC clock 2-31
_VAL2FLD(RCC_CFGR_MCO1, 3)| // Microcontroller clock output PLL clock selected
_VAL2FLD(RCC_CFGR_MCO1PRE, 7); // MCO1 prescaler 111: division by 5
RCC->DCKCFGR2 = _VAL2FLD(RCC_DCKCFGR2_USART1SEL, 0)| // APB2 clock (PCLK2) is selected as USART 1 clock
_VAL2FLD(RCC_DCKCFGR2_USART1SEL, 1)|// Low-power timer1 10: HSI clock is selected
_VAL2FLD(RCC_DCKCFGR2_CK48MSEL, 0)| // 48MHz clock from PLL is selected
_VAL2FLD(RCC_DCKCFGR2_SDMMC1SEL, 0); // 48 MHz clock is selected as SDMMC clock
while(! (RCC->CR & RCC_CR_HSIRDY));
while(! (RCC->CR & RCC_CR_HSERDY));
__DMB();
FLASH->ACR = 7 /// Latency >210mg
| FLASH_ACR_ARTEN /// вкл кеш флеша
| FLASH_ACR_PRFTEN;
while(! (RCC->CR & RCC_CR_PLLRDY));
while(! (RCC->CR & RCC_CR_PLLSAIRDY));
RCC->CFGR |= RCC_CFGR_SW_PLL; // PLL selected as system clock
Пт янв 28, 2022 20:15:15
VAL2FLD
I2C1->TRISE= 15; //100
I2C2->CCR|=I2C_CCR_FS ;
I2C1->CCR=41;
I2C1->CR2|= _VAL2FLD(I2C_CR2_FREQ,50);
I2C1->CCR|=I2C_CCR_FS ;
I2C1->TRISE= 8; //100
I2C2->CCR|=I2C_CCR_FS ;
I2C1->CCR=25;
Пт янв 28, 2022 21:41:38
ivan dimir писал(а):А так выводит.на 400 кГц
Пт янв 28, 2022 22:05:02
https://mcu.goodboard.ru/viewtopic.php?id=11
Сб янв 29, 2022 00:05:42
Сб янв 29, 2022 08:49:19
Сб янв 29, 2022 09:35:36
FLASH->ACR = FLASH_ACR_PRFTEN
| FLASH_ACR_ICEN
| FLASH_ACR_DCEN
| FLASH_ACR_LATENCY_3WS;
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16)
| RCC_CR_HSION
| RCC_CR_HSEON; //Включаем HSE = 8 MHz
while(!(RCC->CR & RCC_CR_HSERDY));
// SYSCLK = 96 МГц USB = 48 МГц
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE
| _VAL2FLD(RCC_PLLCFGR_PLLQ,4)
| _VAL2FLD(RCC_PLLCFGR_PLLN,96)
| _VAL2FLD(RCC_PLLCFGR_PLLM,4)
| RCC_PLLCFGR_PLLP_div2;
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16)
| RCC_CR_HSION
| RCC_CR_HSEON
| RCC_CR_PLLON; //Включаем PLL
while(!(RCC->CR & RCC_CR_PLLRDY));
RCC->CFGR = RCC_CFGR_MCO2_HSE
| RCC_CFGR_MCO2PRE_div1
| RCC_CFGR_MCO1PRE_div1
| RCC_CFGR_I2SSRC_PLLI2S
| RCC_CFGR_MCO1_HSE
| _VAL2FLD(RCC_CFGR_RTCPRE,8)
| RCC_CFGR_PPRE2_DIV1
| RCC_CFGR_PPRE1_DIV2
| RCC_CFGR_HPRE_DIV1
| RCC_CFGR_SW_PLL;
#define RCC_PLLCFGR_PLLP_div2 (0x0U << RCC_PLLCFGR_PLLP_Pos)
#define RCC_PLLCFGR_PLLP_div4 (0x1U << RCC_PLLCFGR_PLLP_Pos)
#define RCC_PLLCFGR_PLLP_div6 (0x2U << RCC_PLLCFGR_PLLP_Pos)
#define RCC_PLLCFGR_PLLP_div8 (0x3U << RCC_PLLCFGR_PLLP_Pos)
#define RCC_CFGR_MCO2_SYSCLK (0x0U << RCC_CFGR_MCO2_Pos)
#define RCC_CFGR_MCO2_PLLI2S (0x1U << RCC_CFGR_MCO2_Pos)
#define RCC_CFGR_MCO2_HSE (0x2U << RCC_CFGR_MCO2_Pos)
#define RCC_CFGR_MCO2_PLL (0x3U << RCC_CFGR_MCO2_Pos)
#define RCC_CFGR_MCO2PRE_div1 (0x0U << RCC_CFGR_MCO2PRE_Pos)
#define RCC_CFGR_MCO2PRE_div2 (0x4U << RCC_CFGR_MCO2PRE_Pos)
#define RCC_CFGR_MCO2PRE_div3 (0x5U << RCC_CFGR_MCO2PRE_Pos)
#define RCC_CFGR_MCO2PRE_div4 (0x6U << RCC_CFGR_MCO2PRE_Pos)
#define RCC_CFGR_MCO2PRE_div5 (0x7U << RCC_CFGR_MCO2PRE_Pos)
#define RCC_CFGR_MCO1PRE_div1 (0x0U << RCC_CFGR_MCO1PRE_Pos)
#define RCC_CFGR_MCO1PRE_div2 (0x4U << RCC_CFGR_MCO1PRE_Pos)
#define RCC_CFGR_MCO1PRE_div3 (0x5U << RCC_CFGR_MCO1PRE_Pos)
#define RCC_CFGR_MCO1PRE_div4 (0x6U << RCC_CFGR_MCO1PRE_Pos)
#define RCC_CFGR_MCO1PRE_div5 (0x7U << RCC_CFGR_MCO1PRE_Pos)
#define RCC_CFGR_I2SSRC_PLLI2S (0x0U << RCC_CFGR_I2SSRC_Pos)
#define RCC_CFGR_I2SSRC_EXT (0x1U << RCC_CFGR_I2SSRC_Pos)
#define RCC_CFGR_MCO1_HSI (0x0U << RCC_CFGR_MCO1_Pos)
#define RCC_CFGR_MCO1_LSE (0x1U << RCC_CFGR_MCO1_Pos)
#define RCC_CFGR_MCO1_HSE (0x2U << RCC_CFGR_MCO1_Pos)
#define RCC_CFGR_MCO1_PLL (0x3U << RCC_CFGR_MCO1_Pos)