Пт май 20, 2022 14:11:56
// setup DMA receiver
static void i2c_DMAr_setup(){
/* Enable the peripheral clock DMA1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN;
DMA1_Channel7->CPAR = (uint32_t)&(I2C1->DR);
DMA1_Channel7->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE;
NVIC_SetPriority(DMA1_Channel7_IRQn, 0);
NVIC_EnableIRQ(DMA1_Channel7_IRQn);
I2C1->CR2 |= I2C_CR2_DMAEN;
i2cDMAr = I2C_DMA_RELAX;
}
/*
* PB10/PB6 - I2C_SCL, PB11/PB7 - I2C_SDA or remap @ PB8 & PB9
* @param withDMA == 1 to setup DMA receiver too
*/
void i2c_setup(uint8_t withDMA){
RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
GPIOB->CRL = (GPIOB->CRL & ~(GPIO_CRL_CNF6 | GPIO_CRL_CNF7)) |
CRL(6, CNF_AFOD | MODE_NORMAL) | CRL(7, CNF_AFOD | MODE_NORMAL);
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
I2C1->CR1 = 0; // clear all previous settings
I2C1->SR1 = 0;
RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST; // reset peripherial
RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C1RST;
I2C1->CR2 = 8; // FREQR=8MHz, T=125ns
//I2C1->CR2 = 10; // FREQR=10MHz, T=100ns
I2C1->TRISE = 9; // (9-1)*125 = 1us
//I2C1->TRISE = 4; // (4-1)*100 = 300ns
I2C1->CCR = 40; // normal mode, 8MHz/2/40 = 100kHz
//I2C1->CCR = I2C_CCR_FS | 10; // fast mode, 10MHz/2/10 = 500kHz
if(withDMA) i2c_DMAr_setup();
I2C1->CR1 |= I2C_CR1_PE; // enable periph
}
/**
* @brief i2c_7bit_receive_DMA - receive data using DMA
* @param data - pointer to external array
* @param nbytes - data len
* @return I2C_OK when receiving started; poll end of receiving by flag i2cDMAr;
*/
i2c_status i2c_7bit_receive_DMA(uint8_t *data, uint16_t nbytes){
if(i2cDMAr == I2C_DMA_BUSY) return I2C_LINEBUSY; // previous receiving still works
if(i2cDMAr == I2C_DMA_NOTINIT) i2c_DMAr_setup();
i2c_status ret = I2C_LINEBUSY;
DBG("Conf DMA");
DMA1_Channel7->CCR &= ~DMA_CCR_EN;
DMA1_Channel7->CMAR = (uint32_t)data;
DMA1_Channel7->CNDTR = nbytes;
// now send address and start I2C receiving
I2C1->SR1 = 0;
I2C1->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
DBG("wait sb");
I2C_WAIT(I2C1->SR1 & I2C_SR1_SB);
(void) I2C1->SR1;
I2C1->DR = addr7r;
DBG("wait addr");
I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR);
if(I2C1->SR1 & I2C_SR1_AF) return I2C_NACK;
(void) I2C1->SR2;
DBG("start");
DMA1_Channel7->CCR |= DMA_CCR_EN;
i2cDMAr = I2C_DMA_BUSY;
ret = I2C_OK;
eotr:
return ret;
}
void dma1_channel7_isr(){
I2C1->CR1 |= I2C_CR1_STOP; // send STOP
DMA1->IFCR = DMA_IFCR_CTCIF7;
DMA1_Channel7->CCR &= ~DMA_CCR_EN;
i2cDMAr = I2C_DMA_READY;
}