Ср май 25, 2022 19:37:27
htim1.Instance = TIM1;
htim1.Init.Prescaler = 8;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 500;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);
TIM1->CCR1 = 400;
Чт май 26, 2022 08:19:47
SystemCoreClockUpdate();
TIM1->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE;
TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE;
TIM1->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E;
TIM1->ARR = SystemCoreClock / 18000;
TIM1->CCR1 = TIM2->ARR * Percent / 100;
Чт май 26, 2022 11:26:57
SystemCoreClockUpdate();
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);
TIM1->CCR1 = 400;
Чт май 26, 2022 13:42:44
TIM1->PSC = 7;
TIM1->ARR = 499;
TIM1->PSC1 = 399;
Чт май 26, 2022 13:51:45
void init_PWM(void)
{
__HAL_RCC_TIM4_CLK_ENABLE();
TMR4.Instance = TIM4;
TMR4.Init.Period = 19999;
TMR4.Init.CounterMode = TIM_COUNTERMODE_UP;
TMR4.Init.Prescaler = 0;
TMR4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
HAL_TIM_PWM_Init (&TMR4); //
PWM4.OCMode = TIM_OCMODE_PWM1;
PWM4.Pulse =10000;
PWM4.OCPolarity = TIM_OCPOLARITY_HIGH;
PWM4.OCFastMode = TIM_OCFAST_ENABLE;
HAL_TIM_PWM_ConfigChannel(&TMR4, &PWM4, TIM_CHANNEL_1);
HAL_TIM_PWM_Start(&TMR4, TIM_CHANNEL_1);
}
void init_servo_port(void) {
__HAL_RCC_GPIOF_CLK_ENABLE();
GPIOF->MODER |= GPIO_MODER_MODE6_1; // Alternate function mode
GPIOF->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6; // very high
GPIOF->PUPDR |= GPIO_PUPDR_PUPD6_1; // pull-down
GPIOF->AFR[0] |= (0x03 << 6 * 4);
}
void init_servo_PWM(void) {
__HAL_RCC_TIM10_CLK_ENABLE();
/* f = 50 Гц. Время периода 20 мс */
TIM10->ARR = (20000 - 1); // период в микросекундах
TIM10->PSC = (120 - 1); // предделитель
TIM10->CCMR1 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; // режим ШИМ1
TIM10->CCMR1 |= TIM_CCMR1_OC1PE; // буферизируем CCR1. необходимо в шиме. Подгрузка осуществляется только после события обновления
TIM10->CCMR1 &= ~TIM_CCMR1_CC1S; //канал на выход
TIM10->CCR1 = TIM10->ARR/2; // коэффициент заполнения 50%
TIM10->CCER &= ~TIM_CCER_CC1P;
TIM10->CCER |= TIM_CCER_CC1E; // активировать выход OC1
TIM10->EGR = TIM_EGR_UG;
TIM10->CR1|= TIM_CR1_CEN; // Запуск таймера
}
Чт май 26, 2022 21:17:16
Сб май 28, 2022 07:06:10
SystemCoreClockUpdate();