Чт дек 01, 2022 11:13:41
AFIO->MAPR |= AFIO_MAPR_CAN_REMAP_REMAP2;
GPIOB->CRH = (GPIOB->CRH & ~(CRH(8,0xf)|CRH(9,0xf))) |
CRH(8, CNF_AFOD | MODE_FAST) | CRH(9, CNF_AFPP | MODE_FAST);
Пт дек 02, 2022 11:47:21
Пт дек 02, 2022 14:39:13
Сб дек 03, 2022 09:10:20
Пн дек 05, 2022 18:55:03
void CAN_setup(uint16_t speed){
LED_off(LED1);
if(speed == 0) speed = oldspeed;
else if(speed < 50) speed = 50;
else if(speed > 3000) speed = 3000;
oldspeed = speed;
uint32_t tmout = 16000000;
// Configure GPIO: PB8 - CAN_Rx, PB9 - CAN_Tx
/* (1) Select AF mode (10) on PB8 and PB9 */
/* (2) AF4 for CAN signals */
RCC->APB2ENR |= RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPBEN;
AFIO->MAPR |= AFIO_MAPR_CAN_REMAP_REMAP2;
GPIOB->CRH = 0;
GPIOB->CRH = (GPIOB->CRH & ~(CRH(8,0xf)|CRH(9,0xf))) |
CRH(8, CNF_FLINPUT | MODE_INPUT) | CRH(9, CNF_AFPP | MODE_NORMAL);
/* Enable the peripheral clock CAN */
RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;
/* Configure CAN */
/* (1) Enter CAN init mode to write the configuration */
/* (2) Wait the init mode entering */
/* (3) Exit sleep mode */
/* (4) Normal mode, set timing to 100kb/s: TBS1 = 4, TBS2 = 3, prescaler = 60 */
/* (5) Leave init mode */
/* (6) Wait the init mode leaving */
/* (7) Enter filter init mode, (16-bit + mask, bank 0 for FIFO 0) */
/* (8) Acivate filter 0 for two IDs */
/* (9) Identifier list mode */
/* (10) Set the Id list */
/* (12) Leave filter init */
/* (13) Set error interrupts enable (& bus off) */
CAN1->MCR |= CAN_MCR_INRQ; /* (1) */
while((CAN1->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) /* (2) */
if(--tmout == 0) break;
CAN1->MCR &=~ CAN_MCR_SLEEP; /* (3) */
CAN1->MCR |= CAN_MCR_ABOM; /* allow automatically bus-off */
CAN1->BTR = 2 << 20 | 3 << 16 | (4500/speed - 1); //| CAN_BTR_SILM | CAN_BTR_LBKM; /* (4) */
CAN1->MCR &= ~CAN_MCR_INRQ; /* (5) */
tmout = 16000000;
while((CAN1->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) /* (6) */
if(--tmout == 0) break;
// accept ALL
CAN1->FMR = CAN_FMR_FINIT; /* (7) */
CAN1->FA1R = CAN_FA1R_FACT0 | CAN_FA1R_FACT1; /* (8) */
// set to 1 all needed bits of CAN1->FFA1R to switch given filters to FIFO1
CAN1->sFilterRegister[0].FR1 = (1<<21)|(1<<5); // all odd IDs
CAN1->FFA1R = 2; // filter 1 for FIFO1, filter 0 - for FIFO0
CAN1->sFilterRegister[1].FR1 = (1<<21); // all even IDs
CAN1->FMR &= ~CAN_FMR_FINIT; /* (12) */
CAN1->IER |= CAN_IER_ERRIE | CAN_IER_FOVIE0 | CAN_IER_FOVIE1 | CAN_IER_BOFIE; /* (13) */
/* Configure IT */
NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0); // RX FIFO0 IRQ
NVIC_SetPriority(CAN1_RX1_IRQn, 0); // RX FIFO1 IRQ
NVIC_SetPriority(CAN1_SCE_IRQn, 0); // RX status changed IRQ
NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
NVIC_EnableIRQ(CAN1_RX1_IRQn);
NVIC_EnableIRQ(CAN1_SCE_IRQn);
CAN1->MSR = 0; // clear SLAKI, WKUI, ERRI
can_status = CAN_READY;
}