Ср фев 08, 2023 18:47:26
module shift_reg(input logic clk,
input logic in,
input logic enable,
output logic out);
reg [2:0] data = 3'b000;
always @(posedge clk) begin
if (enable)
data <= { in, data[2:1] };
end
assign out = in ^ data[2] ^ data[0];
endmodule
data <= { in, data[2:1] };
data <= { data[2:1], in };
data <= { in, data[1:0],};
Чт фев 09, 2023 18:05:18
// ----------
// Created: 2023-02-09 17:55:39
// Generated by MATLAB 9.1 and HDL Coder 3.9
// ----------
// Module: shift_reg
// Source Path: untitled/shift_reg
// Hierarchy Level: 0
// ----------
`timescale 1 ns / 1 ns
module shift_reg
(
clk,
reset,
clk_enable,
In,
ce_out,
Out
);
input clk;
input reset;
input clk_enable;
input In;
output ce_out;
output Out;
wire enb;
reg data_2_out1;
reg [0:1] data_0_reg; // ufix1 [2]
wire [0:1] data_0_reg_next; // ufix1 [2]
wire data_0_out1;
wire XOR1_out1;
wire XOR2_out1;
assign enb = clk_enable;
always @(posedge clk or posedge reset)
begin : data_2_process
if (reset == 1'b1) begin
data_2_out1 <= 1'b0;
end
else begin
if (enb) begin
data_2_out1 <= In;
end
end
end
always @(posedge clk or posedge reset)
begin : data_0_process
if (reset == 1'b1) begin
data_0_reg[0] <= 1'b0;
data_0_reg[1] <= 1'b0;
end
else begin
if (enb) begin
data_0_reg[0] <= data_0_reg_next[0];
data_0_reg[1] <= data_0_reg_next[1];
end
end
end
assign data_0_out1 = data_0_reg[1];
assign data_0_reg_next[0] = data_2_out1;
assign data_0_reg_next[1] = data_0_reg[0];
assign XOR1_out1 = data_2_out1 ^ In;
assign XOR2_out1 = data_0_out1 ^ XOR1_out1;
assign Out = XOR2_out1;
assign ce_out = clk_enable;
endmodule // shift_reg
Чт фев 09, 2023 20:49:50
module flop(input logic clk, reset, in, output logic out);
always @(posedge clk, posedge reset)
if (reset) out <= 1'b0;
else out <= in;
endmodule
module multiplier(input logic clk, reset, in,
output logic out);
wire w0, w1, w2;
flop f0(clk, reset, in, w0);
flop f1(clk, reset, w0, w1);
flop f2(clk, reset, w1, w2);
assign out = in ^ w0 ^ w2;
endmodule
module shift_reg_tb();
logic clk, in, enable, out;
shift_reg r(clk, in, enable, out);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
clk = 1;
enable = 1;
in = 1; #10
$display(out);
in = 0; #10
$display(out);
in = 1; #10
$display(out);
in = 0; #10
$display(out);
in = 0; #10
$display(out);
in = 0; #10
$display(out);
end
endmodule
Пн фев 13, 2023 18:14:45
Чт мар 30, 2023 19:05:55
module multiplier(
input logic clk,
input logic reset,
input logic in,
output logic out
);
reg [2:0] s;
always @(posedge clk)
if (reset)
s <= '0;
else begin
s[2] <= in;
s[1] <= s[2];
s[0] <= s[1];
end
assign out = in ^ s[2] ^ s[0];
endmodule
module multiplier_tb();
logic clk;
logic reset;
logic in;
logic out;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
multiplier m(clk, reset, in, out);
initial begin
#1 reset = 1; #10
reset = 0;
/*
// data 11111
in = 1; #10
in = 1; #10
in = 1; #10
in = 1; #10
in = 1; #10
// tail
in = 0; #10
in = 0; #10
in = 0; #10
$stop;
*/
// data 1000
in = 1; #10
in = 0; #10
in = 0; #10
in = 0; #10
// tail
in = 0; #10
in = 0; #10
in = 0; #10
$stop;
end
always @(posedge clk)
#2 $write(out);
endmodule