Вс дек 15, 2019 09:37:12
RCC->CR |= ((uint32_t)RCC_CR_HSEON);//запускаем HSE (RCC->CR)
while(!(RCC->CR & RCC_CR_HSERDY));//ждем запуска HSE (RCC->CR)
RCC->PLLCFGR = 0x403208;
RCC->CR |= RCC_CR_PLLON;
while((RCC->CR & RCC_CR_PLLRDY) == 0) {}
FLASH->ACR = 3;
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16) | RCC_CR_HSION | RCC_CR_HSEON; //Включаем HSE
while(!(RCC->CR & RCC_CR_HSERDY)); //Ждем запуска HSE
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | _VAL2FLD(RCC_PLLCFGR_PLLR,2) | _VAL2FLD(RCC_PLLCFGR_PLLQ,4) |
_VAL2FLD(RCC_PLLCFGR_PLLP,0) | _VAL2FLD(RCC_PLLCFGR_PLLN,100) | _VAL2FLD(RCC_PLLCFGR_PLLM,4);
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16) | RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_PLLON; //Включаем PLL
while(!(RCC->CR & RCC_CR_PLLRDY)); //Ждем запуска PLL
FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY_3WS;
RCC->CFGR = RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV1 | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
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static uint8_t flag = 1;
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Вс дек 15, 2019 11:45:15
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
if( !(i & (1<<bit)) )
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FMC_BANK1->RAM = rgbe;
Вс дек 15, 2019 20:49:15
Пн дек 16, 2019 11:50:46