Чт мар 09, 2017 13:08:56
NebelWefer писал(а):а вот есть ли данные по чтению?
Пт мар 10, 2017 12:44:57
Пт мар 10, 2017 12:55:16
Вс мар 12, 2017 05:21:58
extern "C"{
void TIM4_IRQHandler(void)
{
if (TIM_GetITStatus(TIM4, TIM_IT_Update) == SET)
{
TIM_ClearITPendingBit(TIM4, TIM_IT_Update);
GPIOB->ODR^=GPIO_Pin_1;
}
}
}
void tim4_config (void)
{
RCC_ClocksTypeDef RCC_Clocks;
RCC_GetClocksFreq(&RCC_Clocks);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
TIM_TimeBaseInitTypeDef TIM_InitStructure;
TIM_TimeBaseStructInit(&TIM_InitStructure);
TIM_InitStructure.TIM_Prescaler = (RCC_Clocks.HCLK_Frequency/1000000 - 1);
TIM_InitStructure.TIM_Period = 1000;
TIM_TimeBaseInit(TIM4, &TIM_InitStructure);
//TIM_Cmd(TIM4, ENABLE);
NVIC_EnableIRQ(TIM4_IRQn);
TIM_ITConfig(TIM4, TIM_IT_Update, ENABLE);
}
Пн мар 20, 2017 11:13:12
Пн мар 20, 2017 18:07:46
Сб апр 01, 2017 09:57:55
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shift_reg IS
PORT
(clk : IN STD_LOGIC ;
data : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
q : OUT STD_LOGIC
);
END shift_reg;
ARCHITECTURE behav OF shift_reg IS
SIGNAL rs: STD_LOGIC_VECTOR (3 downto 0) ;
SIGNAL rscopy: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
process (clk, reset) begin
if (reset = '0') then
rs <= "0000";
else
if (clk'event and clk='1') then rscopy<=rs; end if;
if (clk'event and clk='0') then rs <= data & rscopy(3 downto 1); end if;
end if;
end process;
q <= rs(0);
END behav;
Сб апр 15, 2017 08:44:54
if (clk'event) then
if (clk='0') then....
else....
end if
end if
process (scl)
begin
if scl'event and scl='0' then
shift_reg <= shift_reg (shift_size-2 downto 0) & sda;
end if;
end process;
process (scl)
begin
if scl'event and scl='1' then
if sda = '1' then
latch_reg <= shift_reg;
end if;
end if;
end process;
Пн апр 17, 2017 12:27:29
Пн апр 17, 2017 19:43:38
Евгений33 писал(а):фьюзы - старт с нулевой задержкой
Вт апр 18, 2017 07:46:13
Пн апр 24, 2017 08:11:36
Вт май 02, 2017 20:21:19
Вт май 02, 2017 20:28:29
The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF.
Вт май 02, 2017 20:33:17
The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF.
Ср май 03, 2017 17:23:18
Ср май 03, 2017 19:29:52
Ср май 03, 2017 20:42:58
Ср май 03, 2017 21:10:34
Ср май 03, 2017 21:17:08